Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–49
Configuration Features
f
For more information about how to connect a JTAG chain with multiple voltages
across the devices in the chain, refer to the IEEE 1149.1 (JTAG) Boundary-Scan Testing
for Cyclone III Devices chapter.
Table 9–15. Dedicated JTAG Pins
Pin
Pin Type
Name
Description
Serial input pin for instructions as well as test and programming data. Data shifts in on the
rising edge of TCK. The TDIpin is powered by the VCCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to VCC.
TDI
TDO
Test data input
Serial data output pin for instructions as well as test and programming data. Data shifts out on
the falling edge of TCK. The pin is tri-stated if data is not being shifted out of the device. The
TDOpin is powered by VCCIO in I/O bank 1. If the JTAG interface is not required on the board, the
JTAG circuitry is disabled by leaving this pin unconnected.
Test data output
Input pin that provides the control signal to determine the transitions of the TAP controller state
machine. Transitions in the state machine occur on the rising edge of TCK. Therefore, TMSmust
Test mode select be set up before the rising edge of TCK. TMSis evaluated on the rising edge of TCK. The TMSpin
TMS
TCK
is powered by the VCCIO supply. If the JTAG interface is not required on the board, the JTAG
circuitry is disabled by connecting this pin to VCC.
Clock input to the BST circuitry. Some operations occur at the rising edge while others occur at
the falling edge. The TCKpin is powered by the VCCIO supply. If the JTAG interface is not
required on the board, the JTAG circuitry is disabled by connecting this pin to GND.
Test clock input
You can download data to the device on the PCB through the USB-Blaster,
MasterBlaster, ByteBlaster II, ByteBlasterMV download cable, and Ethernet-Blaster
communications cable during JTAG configuration. Configuring devices using a cable
is similar to programming devices in-system. Figure 9–24 and Figure 9–25 show the
JTAG configuration of a single Cyclone III device family.
For device VCCIO of 2.5, 3.0, and 3.3 V, refer to Figure 9–24. All I/O inputs must
maintain a maximum AC voltage of 4.1 V. Because JTAG pins do not have the internal
PCI clamping diodes to prevent voltage overshoot when using VCCIO of 2.5, 3.0, and
3.3 V, you must power up the VCC of the download cable with a 2.5-V supply from
V
CCA, and you must pull TCKto ground.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
