Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–47
Configuration Features
FPP Configuration Timing
Figure 9–23 shows the timing waveform for FPP configuration when using an
external host.
(1)
Figure 9–23. FPP Configuration Timing Waveform
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
(5)
Byte 2
Byte 3
Byte n-1
Byte 0
Byte 1
Byte n
DATA[7..0]
User Mode
User Mode
tDSU
User I/O Tri-stated with internal pull-up resistor
INIT_DONE
tCD2UM
Notes to Figure 9–23:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONE
are at logic-high levels. When nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power-up, the Cyclone III device family holds nSTATUSlow during POR delay.
(3) After power-up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. It must be driven high or low, whichever is more convenient.
(5) DATA[7..0]is available as user I/O pin after configuration; the state of the pin depends on the dual-purpose pin
settings.
Table 9–14 lists the FPP configuration timing parameters for Cyclone III device family.
Table 9–14. FPP Timing Parameters for Cyclone III Device Family (Part 1 of 2)
Symbol
tCF2CD
tCF2ST0
tCFG
Parameter
nCONFIGlow to CONF_DONElow
nCONFIGlow to nSTATUSlow
nCONFIGlow pulse width
Minimum
Maximum
500
Unit
ns
—
—
500
ns
500
45
—
ns
(1)
tSTATUS
tCF2ST1
tCF2CK
tST2CK
tDSU
nSTATUSlow pulse width
230
s
s
s
s
ns
(1)
nCONFIGhigh to nSTATUShigh
nCONFIGhigh to first rising edge on DCLK
nSTATUShigh to first rising edge of DCLK
DATAsetup time before rising edge on DCLK
DATAhold time after rising edge on DCLK
DCLKhigh time
—
230
(1)
230
—
—
—
—
—
—
—
2
5
tDH
0
ns
tCH
3.2
3.2
7.5
—
300
ns
tCL
DCLKlow time
ns
tCLK
DCLKperiod
ns
(3)
fMAX
DCLKfrequency
100
MHz
s
(2)
tCD2UM
CONF_DONEhigh to user mode
650
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1