9–44
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
Cyclone III device family receives configuration data on the DATA[7..0]pins and the
clock is received on the DCLKpin. Data is latched into the device on the rising edge of
DCLK. Data is continuously clocked into the target device until CONF_DONEgoes high.
The CONF_DONEpin goes high one byte early in FPP configuration mode. The last byte
is required for serial configuration (AS and PS) modes.
1
Two DCLKfalling edges are required after CONF_DONEgoes high to begin the
initialization of the device.
Supplying a clock on CLKUSRdoes not affect the configuration process. After the
CONF_DONEpin goes high, CLKUSRis enabled after the time specified as tCD2CU. After
this time period elapses, Cyclone III device family requires certain amount of clock
cycles to initialize properly and enter user mode. For more information about the
initialization clock cycles required in the Cyclone III device family, refer to Table 9–5
on page 9–10. For more information about the supported CLKUSRfMAX value for
Cyclone III device family, refer to Table 9–14 on page 9–47.
The INIT_DONEpin is released and pulled high when initialization is complete. The
external host device must be able to detect this low-to-high transition which signals
the device has entered user mode. When initialization is complete, the device enters
user mode. In user mode, the user I/O pins no longer have weak pull-up resistors and
function as assigned in your design.
To ensure that DCLKand DATA[0]are not left floating at the end of the configuration,
the MAX II device must drive them either high or low, whichever is convenient on
your board. The DATA[0]pin is available as a user I/O pin after configuration. When
you choose the FPP scheme in the Quartus II software, the DATA[0]pin is tri-stated by
default in user mode and must be driven by the external host device. To change this
default option in the Quartus II software, select the Dual-Purpose Pins tab of the
Device and Pin Options dialog box.
The DCLKspeed must be below the specified system frequency to ensure correct
configuration. No maximum DCLKperiod exists, which means you can pause
configuration by halting DCLKfor an indefinite amount of time.
If a configuration error occurs during configuration and the Auto-restart
configuration after error option is turned on, the Cyclone III device family releases
nSTATUSafter a reset time-out period (a maximum of 230 s). After nSTATUSis released
and pulled high by a pull-up resistor, the external host device can try to reconfigure
the target device without needing to pulse nCONFIGlow. If this option is turned off, the
external host device must generate a low-to-high transition (with a low pulse of at
least 500 ns) on nCONFIGto restart the configuration process.
The external host device can also monitor the CONF_DONEand INIT_DONEpins to ensure
successful configuration. The CONF_DONEpin must be monitored by the external device
to detect errors and to determine when programming is complete. If all configuration
data is sent but CONF_DONEor INIT_DONEhas not gone high, the external device must
reconfigure the target device.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
