欢迎访问ic37.com |
会员登录 免费注册
发布采购

DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号DPCLK0的Datasheet PDF文件第185页浏览型号DPCLK0的Datasheet PDF文件第186页浏览型号DPCLK0的Datasheet PDF文件第187页浏览型号DPCLK0的Datasheet PDF文件第188页浏览型号DPCLK0的Datasheet PDF文件第190页浏览型号DPCLK0的Datasheet PDF文件第191页浏览型号DPCLK0的Datasheet PDF文件第192页浏览型号DPCLK0的Datasheet PDF文件第193页  
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family  
9–31  
Configuration Features  
Figure 9–11 shows the AP configuration with multiple bus masters.  
Figure 9–11. AP Configuration with Multiple Bus Masters  
(6)  
Other Master Device  
V
CCIO  
(1)  
V
CCIO  
(1) V  
CCIO  
(1)  
#V  
IAT  
10 k  
K
T
#
#
D
#
W
 :
:
O
nOCNFIG  
10 k  
10 k  
UTS  
A
SnT  
CnONFGI  
nCE  
FC_DOEN  
10 k  
nCEO  
(2)  
GND  
CLK  
RST#  
CE#  
DCLK (5)  
nRESET  
FLASH_nCE  
nOE  
nAVD  
OE#  
ADV#  
WE#  
WAIT  
MSEL[3..0]  
(3)  
nWE  
I/O (4)  
DATA[15..0] (5)  
PADD[23..0]  
DQ[15:0]  
A[24:1]  
Micron P30/P33 Flash  
Cyclone III Master Device  
Notes to Figure 9–11:  
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.  
(2) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.  
(3) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect MSEL[3..0], refer to Table 9–7 on page 9–11.  
Connect the MSEL pins directly to VCCA or GND.  
(4) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,  
you can optionally use the normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.  
(5) When cascading Cyclone III devices in a multi-device AP configuration, connect the repeater buffers between the master device and slave devices  
for DATA[15..0]and DCLK. All I/O inputs must maintain a maximum AC voltage of 4.1 V. The output resistance of the repeater buffers must fit  
the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.  
(6) The other master device must fit the maximum overshoot equation outlined in “Configuration and JTAG Pin I/O Requirements” on page 9–7.  
(7) The other master device can control the AP configuration bus by driving the nCE pin to high with an output high on the I/O pin.  
(8) The other master device can pulse nCONFIGif it is under system control rather than tied to VCCIO  
.
August 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
 复制成功!