9–28
Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
Configuration Features
The following are the configurations for the DATA[15..0]bus in a multi-device AP
configuration:
■
Byte-wide multi-device AP configuration
Word-wide multi-device AP configuration
■
Byte-Wide Multi-Device AP Configuration
The simpler method for multi-device AP configuration is the byte-wide multi-device
AP configuration. In the byte-wide multi-device AP configuration, the LSB of the
DATA[7..0]pin from the flash and master device (set to the AP configuration scheme)
is connected to the slave devices set to the FPP configuration scheme, as shown in
Figure 9–9.
Figure 9–9. Byte-Wide Multi-Device AP Configuration
V
(1)
V
CCIO
V
CCIO
(1)
V
CCIO
(1)
(2)
V
CCIO
(2)
10 k
Ω
CCIO
10 kΩ
10 kΩ
10 kΩ
10 kΩ
S
S
TUS
A
A
A
T
T
nST
F
F
nOCNFIG
O
O
C_FDONE
nCE
nCEO
nCE
nCEO
nCE
nCEO
N.C. (3)
GND
CLK
RST#
CE#
DCLK
nRESET
FLASH_nCE
nOE
nAVD
OE#
ADV#
WE#
WAIT
MSEL[3..0]
MSEL[3..0]
MSEL[3..0]
(4)
DQ[7..0]
(4)
DQ[7..0]
(4)
nWE
I/O (5)
DATA[15..0]
PADD[23..0]
DATA[7..0]
DCLK
DATA[7..0]
DCLK
DQ[15:0]
A[24:1]
Micron P30/P33 Flash
Cyclone III Master Device
Cyclone III Slave Device
Cyclone III Slave Device
Buffers (6)
Notes to Figure 9–9:
(1) Connect the pull-up resistors to the VCCIO supply of the bank in which the pin resides.
(2) Connect the pull-up resistor to the VCCIO supply voltage of the I/O bank in which the nCEpin resides.
(3) The nCEOpin is left unconnected or used as a user I/O pin when it does not feed the nCEpin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. You must set the master device in AP mode and the slave
devices in FPP mode. To connect MSEL[3..0]for the master device in AP mode and the slave devices in FPP mode, refer to Table 9–7 on
page 9–11. Connect the MSEL pins directly to VCCA or GND.
(5) The AP configuration ignores the WAITsignal during configuration mode. However, if you are accessing flash during user mode with user logic,
you can optionally use the normal I/O to monitor the WAITsignal from the Micron P30 or P33 flash.
(6) Connect the repeater buffers between the master device and slave devices for DATA[15..0]and DCLK. All I/O inputs must maintain a maximum
AC voltage of 4.1 V. The output resistance of the repeater buffers must fit the maximum overshoot equation outlined in “Configuration and JTAG
Pin I/O Requirements” on page 9–7.
Cyclone III Device Handbook
Volume 1
August 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
