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DPCLK0 参数 Datasheet PDF下载

DPCLK0图片预览
型号: DPCLK0
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 1: Cyclone III Device Family Overview  
1–3  
Cyclone III Device Family Features  
Wide collection of pre-built and verified IP cores from Altera and Altera  
Megafunction Partners Program (AMPP) partners  
Supports high-speed external memory interfaces such as DDR, DDR2,  
SDR SDRAM, and QDRII SRAM  
Auto-calibrating PHY feature eases the timing closure process and eliminates  
variations with PVT for DDR, DDR2, and QDRII SRAM interfaces  
Cyclone III device family supports vertical migration that allows you to migrate your  
device to other devices with the same dedicated pins, configuration pins, and power  
pins for a given package-across device densities. This allows you to optimize device  
density and cost as your design evolves.  
Table 1–1 lists Cyclone III device family features.  
Table 1–1. Cyclone III Device Family Features  
Number of  
Global  
Clock  
Networks  
Logic  
Elements  
Total RAM  
Bits  
18 x 18  
Multipliers  
Maximum  
User I/Os  
Family  
Device  
M9K  
PLLs  
Blocks  
EP3C5  
EP3C10  
5,136  
10,320  
15,408  
24,624  
39,600  
55,856  
81,264  
119,088  
70,208  
100,448  
150,848  
198,464  
46  
46  
423,936  
423,936  
23  
23  
2
2
4
4
4
4
4
4
4
4
4
4
10  
10  
20  
20  
20  
20  
20  
20  
20  
20  
20  
20  
182  
182  
346  
215  
535  
377  
429  
531  
429  
429  
429  
429  
EP3C16  
56  
516,096  
56  
EP3C25  
66  
608,256  
66  
Cyclone III  
EP3C40  
126  
260  
305  
432  
333  
483  
666  
891  
1,161,216  
2,396,160  
2,810,880  
3,981,312  
3,068,928  
4,451,328  
6,137,856  
8,211,456  
126  
156  
244  
288  
200  
276  
320  
396  
EP3C55  
EP3C80  
EP3C120  
EP3CLS70  
EP3CLS100  
EP3CLS150  
EP3CLS200  
Cyclone III  
LS  
July 2012 Altera Corporation  
Cyclone III Device Handbook  
Volume 1  
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