Stratix II Architecture
Figure 2–38. Regional Clock Control Blocks
CLKp
Pin
CLKn
Pin
(2)
PLL Counter
Outputs (3)
2
Internal
Logic
Static Clock Select
(1)
Enable/
Disable
Internal
Logic
RCLK
Notes to Figure 2–38:
(1) These clock select signals can only be set through a configuration file (.sof or .pof)
and cannot be dynamically controlled during user mode operation.
(2) Only the CLKnpins on the top and bottom of the device feed to regional clock select
blocks.The clock outputs from corner PLLs cannot be dynamically selected
through the global clock control block.
(3) The clock outputs from corner PLLs cannot be dynamically selected through the
global clock control block.
Altera Corporation
May 2007
2–55
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
