I/O Structure
Table 2–17 shows the Stratix II on-chip termination support per I/O bank.
Table 2–17. On-Chip Termination Support by I/O Banks (Part 1 of 2)
On-Chip Termination Support
I/O Standard Support
Top & Bottom Banks
Left & Right Banks
Series termination without
calibration
3.3-V LVTTL
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
v
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I and II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL
v
v
2–90
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
