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CLK3_1N 参数 Datasheet PDF下载

CLK3_1N图片预览
型号: CLK3_1N
PDF下载: 下载PDF文件 查看货源
内容描述: 的Cyclone III器件手册 [Cyclone III Device Handbook]
分类和应用:
文件页数/大小: 274 页 / 7302 K
品牌: ALTERA [ ALTERA CORPORATION ]
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10–2  
Chapter 10: Hot-Socketing and Power-On Reset in the Cyclone III Device Family  
Hot-Socketing Specifications  
Devices Driven Before Power-Up  
You can drive signals into I/O pins, dedicated input pins, and dedicated clock pins of  
Cyclone III device family before or during power-up or power down without  
damaging the device. The Cyclone III device family supports any power-up or  
power down sequence (VCCIO, VCCINT) to simplify system level design.  
I/O Pins Remain Tristated During Power-Up  
The output buffers of Cyclone III device family are turned off during system  
power up or power down. Cyclone III device family does not drive out until the  
device is configured and working in recommended operating conditions. The I/O  
pins are tristated until the device enters user mode with a weak pull-up resistor (R) to  
VCCIO  
.
You can power-up or power down the VCCIO, VCCA, and VCCINT pins in any sequence.  
The VCCIO, VCCA, and VCCINT pins must have a monotonic rise to their steady state  
levels. The maximum power ramp rate is 3 ms for fast POR time and 50 ms for  
standard POR time. The minimum power ramp rate is 50 µs. VCCIO for all I/O banks  
must be powered up during device operation. All VCCA pins must be powered to 2.5 V  
(even when PLLs are not used), and must be powered up and powered down at the  
same time. VCCD_PLL must always be connected to VCCINT through a decoupling  
capacitor and ferrite bead. During hot-socketing, the I/O pin capacitance is less than  
15 pF and the clock pin capacitance is less than 20 pF.  
Cyclone III device family meets the following hot-socketing specification:  
The hot-socketing DC specification is | IIOPIN | < 300 uA  
The hot-socketing AC specification is | IIOPIN | < 8 mA for the ramp rate of 10 ns  
or more  
For ramp rates faster than 10 ns on I/O pins, |IIOPIN| is obtained with the equation  
I = C dv/dt, in which C is the I/O pin capacitance and dv/dt is the slew rate. The  
hot-socketing specification takes into account the pin capacitance but not board trace  
and external loading capacitance. You must consider additional or separate  
capacitance for trace, connector, and loading. IIOPIN is the current for any user I/O  
pins on the device. The DC specification applies when all VCC supplied to the device is  
stable in the powered-up or powered-down conditions.  
A possible concern for semiconductor devices in general regarding hot-socketing is  
the potential for latch up. Latch up can occur when electrical subsystems are  
hot-socketed into an active system. During hot-socketing, the signal pins may be  
connected and driven by the active system before the power supply can provide  
current to the VCC of the device and ground planes. This condition can lead to latch up  
and cause a low-impedance path from VCC to ground in the device. As a result, the  
device extends a large amount of current, possibly causing electrical damage.  
The design of the I/O buffers and hot-socketing circuitry ensures that Cyclone III  
device family are immune to latch up during hot-socketing.  
f
For more information about the hot-socketing specification, refer to the Cyclone III  
Device Data Sheet and Cyclone III LS Device Data Sheet chapters and the Hot-Socketing  
and Power-Sequencing Feature and Testing for Altera Devices white paper.  
Cyclone III Device Handbook  
Volume 1  
July 2012 Altera Corporation  
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