8–12
Chapter 8: External Memory Interfaces in the Cyclone III Device Family
Cyclone III Device Family Memory Interfaces Features
DDR Output Registers
A dedicated write DDIO block is implemented in the DDR output and output enable
paths. Figure 8–5 shows how Cyclone III device family dedicated write DDIO block is
implemented in the I/O element (IOE) registers.
Figure 8–5. Cyclone III Device Family Dedicated Write DDIO
DDR Output Enable Registers
Output Enable
IOE
Register
Output Enable
Register AOE
data1
data0
IOE
Register
Output Enable
Register BOE
DDR Output Registers
datain_l
IOE
Register
data0
data1
DQ or DQS
Output Register AO
datain_h
IOE
Register
-90° Shifted Clock
®
Output Register BO
The two DDR output registers are located in the I/O element (IOE) block. Two serial
data streams routed through datain_land datain_h, are fed into two registers,
outputregister Aoand outputregister Bo, respectively, on the same clock edge.
The output from outputregisterAois captured on the falling edge of the clock, while
the output from outputregisterBois captured on the rising edge of the clock. The
registered outputs are multiplexed by the common clock to drive the DDR output pin
at twice the data rate.
The DDR output enable path has a similar structure to the DDR output path in the
IOE block. The second output enable register provides the write preamble for the DQS
strobe in DDR external memory interfaces. This active-low output enable register
extends the high-impedance state of the pin by half a clock cycle to provide the
external memory’s DQSwrite preamble time specification.
Cyclone III Device Handbook
Volume 1
July 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
