Chapter 2: Logic Elements and Logic Array Blocks in the Cyclone III Device Family
2–3
LE Operating Modes
In addition to the three general routing outputs, LEs in a LAB have register chain
outputs, which allows registers in the same LAB to cascade together. The register
chain output allows the LUTs to be used for combinational functions and the registers
to be used for an unrelated shift register implementation. These resources speed up
connections between LABs while saving local interconnect resources.
LE Operating Modes
Cyclone III device family LEs operate in the following modes:
■
■
Normal mode
Arithmetic mode
LE operating modes use LE resources differently. In each mode, there are six available
inputs to the LE. These inputs include the four data inputs from the LAB local
interconnect, the LE carry-in from the previous LE carry-chain, and the register chain
connection. Each input is directed to different destinations to implement the desired
logic function. LAB-wide signals provide clock, asynchronous clear, synchronous
clear, synchronous load, and clock enable control for the register. These LAB-wide
signals are available in all LE modes.
The Quartus® II software automatically chooses the appropriate mode for common
functions, such as counters, adders, subtractors, and arithmetic functions, in
conjunction with parameterized functions such as the library of parameterized
modules (LPM) functions. You can also create special-purpose functions that specify
which LE operating mode to use for optimal performance, if required.
Normal Mode
Normal mode is suitable for general logic applications and combinational functions.
In normal mode, four data inputs from the LAB local interconnect are inputs to a
four-input LUT (Figure 2–2). The Quartus II Compiler automatically selects the
carry-in (cin) or the data3signal as one of the inputs to the LUT. LEs in normal mode
support packed registers and register feedback.
Figure 2–2 shows LEs in normal mode.
Figure 2–2. Cyclone III Device Family LEs in Normal Mode
Register Chain
Connection
sload
sclear
(LAB Wide) (LAB Wide)
Packed Register Input
Row, Column, and
Direct Link Routing
Q
D
data1
data2
Row, Column, and
Direct Link Routing
ENA
data3
cin (from cout
of previous LE)
CLRN
Four-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
Local Routing
data4
Register
Chain Output
Register Bypass
Register Feedback
December 2011 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
