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CLK12P 参数 Datasheet PDF下载

CLK12P图片预览
型号: CLK12P
PDF下载: 下载PDF文件 查看货源
内容描述: 的Stratix II器件手册,卷1 [Stratix II Device Handbook, Volume 1]
分类和应用:
文件页数/大小: 768 页 / 5210 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Stratix II Architecture  
The DSP block is divided into four block units that interface with four  
LAB rows on the left and right. Each block unit can be considered one  
complete 18 × 18-bit multiplier with 36 inputs and 36 outputs. A local  
interconnect region is associated with each DSP block. Like an LAB, this  
interconnect region can be fed with 16 direct link interconnects from the  
LAB to the left or right of the DSP block in the same row. R4 and C4  
routing resources can access the DSP block's local interconnect region.  
The outputs also work similarly to LAB outputs as well. Eighteen outputs  
from the DSP block can drive to the left LAB through direct link  
interconnects and eighteen can drive to the right LAB though direct link  
interconnects. All 36 outputs can drive to R4 and C4 routing  
interconnects. Outputs can drive right- or left-column routing.  
Figures 2–29 and 2–30 show the DSP block interfaces to LAB rows.  
Figure 2–29. DSP Block Interconnect Interface  
DSP Block  
OA[17..0]  
OB[17..0]  
R4, C4 & Direct  
R4, C4 & Direct  
Link Interconnects  
Link Interconnects  
A1[17..0]  
B1[17..0]  
OC[17..0]  
OD[17..0]  
A2[17..0]  
B2[17..0]  
OE[17..0]  
OF[17..0]  
A3[17..0]  
B3[17..0]  
OG[17..0]  
OH[17..0]  
A4[17..0]  
B4[17..0]  
Altera Corporation  
May 2007  
2–45  
Stratix II Device Handbook, Volume 1  
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