TriMatrix Memory
Figure 2–26. M-RAM Row Unit Interface to Interconnect
C4 Interconnect
R4 and R24 Interconnects
M-RAM Block
LAB
Up to 16
dataout_a[ ]
16
datain_a[ ]
addressa[ ]
addr_ena_a
renwe_a
Up to 28
Direct Link
Interconnects
byteena [ ]
A
clocken_a
clock_a
aclr_a
Row Interface Block
M-RAM Block to
LAB Row Interface
Block Interconnect Region
Table 2–4 shows the input and output data signal connections along with
the address and control signal input connections to the row unit interfaces
(L0 to L5 and R0 to R5).
2–38
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
