TriMatrix Memory
Figure 2–20. M512 RAM Block LAB Row Interface
C4 Interconnect
R4 Interconnect
16
Direct link
Direct link
interconnect
to adjacent LAB
interconnect
to adjacent LAB
dataout
Direct link
Direct link
M512 RAM
interconnect
interconnect
Block
from adjacent LAB
from adjacent LAB
clocks
datain
control
signals
address
2
6
M512 RAM Block Local LAB Row Clocks
Interconnect Region
M4K RAM Blocks
The M4K RAM block includes support for true dual-port RAM. The M4K
RAM block is used to implement buffers for a wide variety of applications
such as storing processor code, implementing lookup schemes, and
implementing larger memory applications. Each block contains 4,608
RAM bits (including parity bits). M4K RAM blocks can be configured in
the following modes:
■
■
■
■
■
■
True dual-port RAM
Simple dual-port RAM
Single-port RAM
FIFO
ROM
Shift register
When configured as RAM or ROM, you can use an initialization file to
pre-load the memory contents.
2–32
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
