DC & Switching Characteristics
Table 5–93. Fast PLL Specifications
Name Description
Min
Typ
Max
Unit
fIN
Input clock frequency (for -3 and -4 speed
grade devices)
16.08
717
MHz
Input clock frequency (for -5 speed grade
devices)
16.08
640
MHz
fINPFD
Input frequency to the PFD
Input clock duty cycle
16.08
40
500
60
MHz
%
fINDUTY
tINJITTER
Input clock jitter tolerance in terms of period
jitter. Bandwidth ≤ 2 MHz
0.5
1.0
ns (p-p)
Input clock jitter tolerance in terms of period
jitter. Bandwidth > 2 MHz
ns (p-p)
MHz
fVCO
Upper VCO frequency range for –3 and –4
speed grades
300
300
150
150
1,040
840
Upper VCO frequency range for –5 speed
grades
MHz
Lower VCO frequency range for –3 and –4
speed grades
520
MHz
Lower VCO frequency range for –5 speed
grades
420
MHz
fOUT
4.6875
150
550
1,040
(1)
MHz
MHz
MHz
PLL output frequency to GCLKor RCLK
PLL output frequency to LVDS or DPA clock
fOUT_IO
PLL clock output frequency to regular I/O
pin
4.6875
fSCANCLK
Scanclk frequency
100
MHz
ns
tCONFIGPLL
Time required to reconfigure scan chains
for fast PLLs
75/fSCANCLK
fCLBW
tLOCK
PLL closed-loop bandwidth
1.16
5.00
0.03
28.00
1.00
MHz
ms
Time required for the PLL to lock from the
time it is enabled or the end of the device
configuration
tPLL_PSERR
Accuracy of PLL phase shift
15
ps
ns
ns
tARESET
10
Minimum pulse width on aresetsignal.
tARESET_RECONFIG
500
Minimum pulse width on the aresetsignal
when using PLL reconfiguration. Reset the
PLL after scandonegoes high.
Note to Table 5–93:
(1) Limited by I/O fMA X. See Table 5–77 on page 5–67 for the maximum.
Altera Corporation
April 2011
5–93
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
