Timing Model
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 3 of 3)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(2)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(3)
1.8-V HSTL
Class I
4 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
972
930
975
933
958
916
962
920
953
911
970
928
974
932
960
918
1018
976
1005
963
1019
976
1610
1555
1580
1525
1576
1521
1567
1512
1566
1511
1591
1536
1579
1524
1572
1517
1723
1668
1723
1668
1689
1632
1658
1601
1653
1596
1644
1587
1643
1586
1669
1612
1657
1600
1649
1592
1808
1751
1808
1751
1850
1787
1816
1753
1811
1748
1801
1738
1800
1737
1828
1765
1815
1752
1807
1744
1980
1917
1980
1917
1956
1883
1920
1847
1916
1843
1905
1832
1904
1831
1933
1860
1919
1846
1911
1838
2089
2016
2089
2016
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
6 mA
8 mA
10 mA
1022
979
1004
961
1008
965
12 mA
(1)
999
956
1.5-V HSTL
Class I
4 mA
6 mA
1018
975
1021
978
8 mA (1) tOP
1006
963
tDIP
tOP
tDIP
tOP
LVDS
1067
1024
1053
1010
HyperTransport
tDIP
Notes to Table 5–76:
(1) This is the default setting in the Quartus II software.
(2) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(3) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Maximum Input & Output Clock Toggle Rate
Maximum clock toggle rate is defined as the maximum frequency
achievable for a clock type signal at an I/O pin. The I/O pin can be a
regular I/O pin or a dedicated clock I/O pin.
5–66
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
ALTERA [ ALTERA CORPORATION ]
