Timing Model
Table 5–75. Stratix II I/O Output Delay for Column Pins (Part 8 of 8)
Minimum Timing
Drive
-3
-3
-4
-5
Speed Speed
Grade Grade
(3)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Strength
Industrial Commercial
(4)
1.5-V
Differential
HSTL Class II
16 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
881
924
946
927
949
929
951
1431
1497
1439
1505
1450
1516
1501
1571
1510
1580
1521
1591
1644
1720
1654
1730
1666
1742
1734
1824
1744
1834
1757
1847
ps
ps
901
884
904
886
906
18 mA
20 mA
Notes to Table 5–75:
(1) This is the default setting in the Quartus II software.
(2) These I/O standards are only supported on DQS pins.
(3) These numbers apply to -3 speed grade EP2S15, EP2S30, EP2S60, and EP2S90 devices.
(4) These numbers apply to -3 speed grade EP2S130 and EP2S180 devices.
Table 5–76. Stratix II I/O Output Delay for Row Pins (Part 1 of 3)
Minimum Timing
-3
-3
-4
-5
Drive
Strength
Speed Speed
Grade Grade
(2)
I/O Standard
Parameter
Speed Speed Unit
Grade Grade
Industrial Commercial
(3)
LVTTL
4 mA
8 mA
tOP
tDIP
tOP
tDIP
tOP
tDIP
tOP
tDIP
1267
1225
1144
1102
1091
1049
1144
1102
1044
1002
1328
1285
1200
1157
1144
1101
1200
1157
1094
1051
2655
2600
2113
2058
2081
2026
2113
2058
1853
1798
2786
2729
2217
2160
2184
2127
2217
2160
1944
1887
3052
2989
2429
2366
2392
2329
2429
2366
2130
2067
3189
3116
2549
2476
2512
2439
2549
2476
2243
2170
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
12 mA
(1)
LVCMOS
4 mA
8 mA (1) tOP
tDIP
5–64
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
