Timing Model
Table 5–36. Stratix II Performance Notes (Part 3 of 6)
Note (1)
Resources Used
Performance
-4
-3
-3
TriMatrix
ALUTs Memory
Blocks
-5
Applications
DSP
Blocks Grade Grade
(2) (3)
Speed Speed
Speed Speed Unit
Grade Grade
DSP
block
9 × 9-bit multiplier (5)
0
0
0
0
1
1
430.29 409.16 373.13 320.10 MHz
410.17 390.01 356.12 305.06 MHz
18 × 18-bit
multiplier (5)
18 × 18-bit
multiplier (7)
0
0
0
0
1
1
1
1
4
9
450.04 428.08 391.23 335.12 MHz
250.00 238.15 217.48 186.60 MHz
410.17 390.01 356.12 305.06 MHz
410.17 390.01 356.12 305.06 MHz
259.06 240.61 217.15 185.01 MHz
398.72 364.03 355.23 306.37 MHz
36 × 36-bit
multiplier (5)
36 × 36-bit multiplier
(6)
0
0
18-bit, four-tap FIR
filter
0
0
Larger
designs
8-bit,16-tap parallel
FIR filter
58
2976
0
8-bit, 1024-point,
streaming, three
22
multipliers and five
adders FFT function
8-bit, 1024-point,
streaming, four
multipliers and two
adders FFT function
2781
984
22
5
12
3
398.56 409.16 347.22 311.13 MHz
425.17 365.76 346.98 292.39 MHz
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst,threemultipliers
and five adders FFT
function
8-bit, 1024-point,
single output, one
parallel FFT engine,
burst, four multipliers
and two adders FFT
function
919
5
4
427.53 378.78 357.14 307.59 MHz
5–30
Altera Corporation
April 2011
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
