DC & Switching Characteristics
Table 5–12. LVPECL Specifications
Symbol
VCCIO (1)
VID
Parameter
Conditions
Minimum
3.135
Typical
3.300
600
Maximum Unit
I/O supply voltage
3.465
1,000
V
Input differential voltage
swing (single-ended)
300
mV
VICM
VOD
Input common mode voltage
1.0
2.5
V
Output differential voltage
(single-ended)
RL = 100 Ω
RL = 100 Ω
525
970
mV
VOCM
RL
Output common mode
voltage
1,650
90
2,250
110
mV
Receiver differential input
resistor
100
Ω
Note to Table 5–12:
(1) The top and bottom clock input differential buffers in I/O banks 3, 4, 7, and 8 are powered by VCCINT, not VCCIO
The PLL clock output/feedback differential buffers are powered by VCC_PLL_OUT. For differential clock
output/feedback operation, VCC_PLL_OUTshould be connected to 3.3 V.
.
Table 5–13. HyperTransport Technology Specifications
Symbol
Parameter
Conditions
Minimum
Typical
Maximum Unit
VCCIO
I/O supply voltage for left and
right I/O banks (1, 2, 5, and 6)
2.375
2.500
2.625
V
VID
Input differential voltage swing RL = 100 Ω
300
600
900
mV
(single-ended)
VICM
VOD
Input common mode voltage
RL = 100 Ω
RL = 100 Ω
385
400
600
600
845
820
mV
mV
Output differential voltage
(single-ended)
Δ VOD
Change in VOD between high
and low
RL = 100 Ω
75
mV
VOCM
Output common mode voltage RL = 100 Ω
440
90
600
100
780
50
mV
mV
Δ VOCM
Change in VOCM between high RL = 100 Ω
and low
RL
Receiver differential input
resistor
110
Ω
Table 5–14. 3.3-V PCI Specifications (Part 1 of 2)
Symbol
VCCIO
VIH
Parameter
Output supply voltage
High-level input voltage
Conditions
Minimum
3.0
Typical
Maximum Unit
3.3
3.6
V
V
0.5 × VCCIO
VCCIO + 0.5
Altera Corporation
April 2011
5–9
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
