Hot Socketing Feature Implementation in Stratix II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for Stratix II Devices
Power On
Reset
Monitor
Output
Weak
Pull-Up
R
Output Enable
Resistor
Voltage
Tolerance
Control
Hot Socket
PAD
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors VCCINT voltage level and keeps I/O pins tri-
stated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to VCCIO is present to keep the I/O pins from floating. The
3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V
before VCCIO and/or VCCINT and/or VCCPD are powered, and it prevents
the I/O pins from driving out when the device is not in user mode. The
hot socket circuit prevents I/O pins from internally powering VCCIO
,
VCCINT, and VCCPD when driven by external signals before the device is
powered.
Figure 4–2 shows a transistor level cross section of the Stratix II device
I/O buffers. This design ensures that the output buffers do not drive
when VCCIO is powered before VCCINT or if the I/O pad voltage is higher
than VCCIO. This also applies for sudden voltage spikes during hot
insertion. There is no current path from signal I/O pins to VCCINT or VCCIO
or VCCPD during hot insertion. The VPAD leakage current charges the 3.3-V
tolerant circuit capacitance.
4–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
