Configuration
The PLL_ENApin and the configuration input pins (Table 3–4) have a
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSELinput pin selects which input buffer is used. The 3.3-
V/2.5-V input buffer is powered by VCCPD, while the 1.8-V/1.5-V input
buffer is powered by VCCIO. Table 3–4 shows the pins affected by VCCSEL.
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
VCCSEL = HIGH (connected
to VCCPD
VCCSEL = LOW (connected
to GND)
Pin
)
nSTATUS(when
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK(when used
as an input)
1.8/1.5-V input buffer is
selected. Input buffer is
powered by VCCIO of the I/O
bank.
3.3/2.5-V input buffer is
selected. Input buffer is
CS
powered by VCCPD
.
nWS
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSELis sampled during power-up. Therefore, the VCCSELsetting
cannot change on the fly or during a reconfiguration. The VCCSELinput
buffer is powered by VCCINT and must be hardwired to VCCPD or ground.
A logic high VCCSELconnection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSELshould be set to
comply with the logic levels driven out of the configuration device or
MAX® II/microprocessor.
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSELto a logic low; you can set the VCCIO of the I/O
bank that contains the configuration inputs to any supported voltage. If
3–6
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007
ALTERA [ ALTERA CORPORATION ]
