IEEE Std. 1149.1 JTAG Boundary-Scan Support
Table 3–1. Stratix II JTAG Instructions
JTAG Instruction
Instruction Code
Description
Allows a snapshot of signals at the device pins to be captured and
examined during normal device operation, and permits an initial
data pattern to be output at the device pins. Also used by the
SignalTap II embedded logic analyzer.
SAMPLE/PRELOAD 00 0000 0101
Allows the external circuitry and board-level interconnects to be
tested by forcing a test pattern at the output pins and capturing test
results at the input pins.
EXTEST(1)
BYPASS
00 0000 1111
11 1111 1111 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation.
USERCODE
00 0000 0111 Selects the 32-bit USERCODEregister and places it between the
TDI and TDOpins, allowing the USERCODEto be serially shifted
out of TDO.
IDCODE
00 0000 0110 Selects the IDCODEregister and places it between TDIand TDO,
allowing the IDCODEto be serially shifted out of TDO.
HIGHZ (1)
00 0000 1011 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation, while
tri-stating all of the I/O pins.
CLAMP (1)
00 0000 1010 Places the 1-bit bypass register between the TDIand TDOpins,
which allows the BST data to pass synchronously through selected
devices to adjacent devices during normal device operation while
holding I/O pins to a state defined by the data in the boundary-scan
register.
ICR instructions
Used when configuring a Stratix II device via the JTAG port with a
USB Blaster, MasterBlaster™, ByteBlasterMV™, or ByteBlaster II
download cable, or when using a .jam or .jbc via an embedded
processor or JRunner.
PULSE_NCONFIG
00 0000 0001 Emulates pulsing the nCONFIGpin low to trigger reconfiguration
even though the physical pin is unaffected.
Allows configuration of I/O standards through the JTAG chain for
JTAG testing. Can be executed before, during, or after
CONFIG_IO (2)
00 0000 1101
configuration. Stops configuration if executed during configuration.
Once issued, the CONFIG_IOinstruction holds nSTATUSlow to
reset the configuration device. nSTATUSis held low until the IOE
configuration register is loaded and the TAP controller state
machine transitions to the UPDATE_DRstate.
SignalTap II
instructions
Monitors internal device operation with the SignalTap II embedded
logic analyzer.
Notes to Table 3–1:
(1) Bus hold and weak pull-up resistor features override the high-impedance state of HIGHZ, CLAMP, and EXTEST.
(2) For more information on using the CONFIG_IOinstruction, see the MorphIO: An I/O Reconfiguration Solution for
Altera Devices White Paper.
3–2
Altera Corporation
May 2007
Stratix II Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
