Chapter 9: Configuration, Design Security, and Remote System Upgrades in the Cyclone III Device Family
9–69
Configuration Features
Table 9–22. Dedicated Configuration Pins on Cyclone III Device Family (Part 4 of 4)
User
Mode
Configuration
Scheme
Pin Name
Pin Type
Description
24-bit address bus from the Cyclone III device to the parallel
flash in AP mode. Connects to the A[24:1]bus on the
Micron P30 or P33 flash.
(3)
PADD[23..0]
I/O
I/O
AP
Output
Active-low reset output. Driving the nRESETpin low resets
the parallel flash. Connects to the RST#pin on the Micron
P30 or P33 flash.
(3)
nRESET
nAVD
AP
Output
Output
Active-low address valid output. Driving the nAVDpin low
during a read or write operation indicates to the parallel flash
that valid address is present on the PADD[23..0]address
bus. Connects to the ADV#pin on the Micron P30 or P33
flash.
(3)
I/O
AP
Active-low output enable to the parallel flash. Driving the nOE
pin low during a read operation enables the parallel flash
outputs (DATA[15..0]). Connects to the OE#pin on the
Micron P30 or P33 flash.
(3)
nOE
I/O
I/O
AP
Output
Output
Active-low write enable to the parallel flash. Driving the nWE
pin low during a write operation indicates to the parallel flash
that data on the DATA[15..0]bus is valid. Connects to the
WE#pin on the Micron P30 or P33 flash.
(3)
nWE
AP
Note to Table 9–22:
(1) If you are accessing the EPCS device with the ALTASMI_PARALLEL megafunction or your own user logic in user mode, in the Device and Pin
Options window of the Quartus II software, in the Dual-Purpose Pins category, select Use as regular I/O for this pin.
(2) To tri-state the AS configuration pins in user mode, turn on the Enable input tri-state on active configuration pins in user mode option from the
Device and Pin Options dialog box in the Configuration tab. This option tri-states the DCLK, DATA0, nCSO, and ASDOpins.
(3) AP configuration scheme is for Cyclone III devices only.
August 2012 Altera Corporation
Cyclone III Device Handbook
Volume 1
ALTERA [ ALTERA CORPORATION ]
