ACEX 1K Programmable Logic Device Family Data Sheet
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-1 speed grade devices are compliant with PCI Local Bus
...and More
Features
Specification, Revision 2.2 for 5.0-V operation
Built-in Joint Test Action Group (JTAG) boundary-scan test
(BST) circuitry compliant with IEEE Std. 1149.1-1990, available
without consuming additional device logic.
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Operate with a 2.5-V internal supply voltage
In-circuit reconfigurability (ICR) via external configuration
devices, intelligent controller, or JTAG port
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ClockLockTM and ClockBoostTM options for reduced clock delay,
clock skew, and clock multiplication
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Built-in, low-skew clock distribution trees
100% functional testing of all devices; test vectors or scan chains
are not required
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Pull-up on I/O pins before and during configuration
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Flexible interconnect
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FastTrack® Interconnect continuous routing structure for fast,
predictable interconnect delays
Dedicated carry chain that implements arithmetic functions such
as fast adders, counters, and comparators (automatically used by
software tools and megafunctions)
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Dedicated cascade chain that implements high-speed,
high-fan-in logic functions (automatically used by software tools
and megafunctions)
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Tri-state emulation that implements internal tri-state buses
Up to six global clock signals and four global clear signals
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Powerful I/O pins
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Individual tri-state output enable control for each pin
Open-drain option on each I/O pin
Programmable output slew-rate control to reduce switching
noise
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Clamp to V
Supports hot-socketing
user-selectable on a pin-by-pin basis
CCIO
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Altera Corporation
ALTERA [ ALTERA CORPORATION ]
