Chapter 3: DC and Switching Characteristics for MAX V Devices
3–19
Timing Model and Specifications
Figure 3–5. UFM Erase Waveform
9 Address Bits
ARShft
ARClk
tACLK
tAH
tASU
tADH
ARDin
DRShft
DRClk
DRDin
DRDout
tADS
OSC_ENA
tOSCS
tOSCH
Program
Erase
tEB
tBE
Busy
tEPMX
Table 3–25. Routing Delay Internal Timing Microparameters for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z
5M1270Z/ 5M2210Z
Routing
Unit
C4
C5, I5
C4
C5, I5
Min
—
Max
860
Min
—
Max
Min
—
Max
561
445
731
Min
—
Max
690
548
899
tC4
1,973
1,479
2,947
ps
ps
ps
tR4
—
655
—
—
—
tLOCAL
—
1,143
—
—
—
External Timing Parameters
External timing parameters are specified by device density and speed grade. All
external I/O timing parameters shown are for the 3.3-V LVTTL I/O standard with the
maximum drive strength and fast slew rate. For external I/O timing using standards
other than LVTTL or for different drive strengths, use the I/O standard input and
output delay adders in Table 3–32 on page 3–23 through Table 3–36 on page 3–25.
f For more information about each external timing parameters symbol, refer to
AN629: Understanding Timing in Altera CPLDs.
May 2011 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
