3–16
Chapter 3: DC and Switching Characteristics for MAX V Devices
Timing Model and Specifications
1
The default slew rate setting for MAX V devices in the Quartus II design software is
“fast”.
Table 3–24. UFM Block Internal Timing Microparameters for MAX V Devices (Part 1 of 2)
5M40Z/ 5M80Z/ 5M160Z/
5M1270Z/ 5M2210Z
5M240Z/ 5M570Z
Symbol
Parameter
Unit
C4
C5, I5
C4 C5, I5
Min
Max
Min
Max
Min
Max
Min
Max
Address register clock
period
tACLK
100
—
100
—
100
—
100
—
ns
ns
Address register shift
signal setup to address
register clock
tASU
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
20
20
20
—
—
—
Address register shift
signal hold to address
register clock
tAH
ns
ns
Address register data in
setup to address register
clock
tADS
Address register data in
hold from address
register clock
tADH
tDCLK
tDSS
20
100
60
—
—
—
20
100
60
—
—
—
20
100
60
—
—
—
20
100
60
—
—
—
ns
ns
ns
Data register clock period
Data register shift signal
setup to data register
clock
Data register shift signal
hold from data register
clock
tDSH
20
20
—
—
20
20
—
—
20
20
—
—
20
20
—
—
ns
ns
Data register data in
setup to data register
clock
tDDS
Data register data in hold
from data register clock
tDDH
tDP
20
0
—
—
20
0
—
—
20
0
—
—
20
0
—
—
ns
ns
Program signal to data
clock hold time
Maximum delay between
program rising edge to
UFM busysignal rising
edge
tPB
—
960
—
960
—
960
—
960
ns
Minimum delay allowed
from UFM busysignal
going low to program
signal going low
tBP
20
—
—
20
—
—
20
—
—
20
—
—
ns
µs
Maximum length of busy
pulse during a program
tPPMX
100
100
100
100
MAX V Device Handbook
May 2011 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
