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5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: MAX V Architecture  
2–15  
MultiTrack Interconnect  
Figure 2–10. R4 Interconnect Connections  
Adjacent LAB can  
drive onto another  
LAB’s R4 Interconnect  
R4 Interconnect  
Driving Right  
C4 Column Interconnects (1)  
R4 Interconnect  
Driving Left  
LAB  
Neighbor  
Primary  
LAB (2)  
LAB  
Neighbor  
Notes to Figure 2–10:  
(1) C4 interconnects can drive R4 interconnects.  
(2) This pattern is repeated for every LAB in the LAB row.  
The column interconnect operates similarly to the row interconnect. Each column of  
LABs is served by a dedicated column interconnect, which vertically routes signals to  
and from LABs and row and column IOEs. These column resources include:  
LUT chain interconnects within an LAB  
Register chain interconnects within an LAB  
C4 interconnects traversing a distance of four LABs in an up and down direction  
MAX V devices include an enhanced interconnect structure within LABs for routing  
LE output to LE input connections faster using LUT chain connections and register  
chain connections. The LUT chain connection allows the combinational output of an  
LE to directly drive the fast input of the LE right below it, bypassing the local  
interconnect. These resources can be used as a high-speed connection for wide fan-in  
functions from LE 1to LE 10in the same LAB. The register chain connection allows  
the register output of one LE to connect directly to the register input of the next LE in  
the LAB for fast shift registers. The Quartus II Compiler automatically takes  
advantage of these resources to improve utilization and performance. Figure 2–11  
shows the LUT chain and register chain interconnects.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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