欢迎访问ic37.com |
会员登录 免费注册
发布采购

5M80ZT100C5 参数 Datasheet PDF下载

5M80ZT100C5图片预览
型号: 5M80ZT100C5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
 浏览型号5M80ZT100C5的Datasheet PDF文件第21页浏览型号5M80ZT100C5的Datasheet PDF文件第22页浏览型号5M80ZT100C5的Datasheet PDF文件第23页浏览型号5M80ZT100C5的Datasheet PDF文件第24页浏览型号5M80ZT100C5的Datasheet PDF文件第26页浏览型号5M80ZT100C5的Datasheet PDF文件第27页浏览型号5M80ZT100C5的Datasheet PDF文件第28页浏览型号5M80ZT100C5的Datasheet PDF文件第29页  
Chapter 2: MAX V Architecture  
2–13  
Logic Elements  
The Quartus II software automatically creates carry chain logic during design  
processing, or you can create it manually during design entry. Parameterized  
functions such as LPM functions automatically take advantage of carry chains for the  
appropriate functions. The Quartus II software creates carry chains longer than 10 LEs  
by linking adjacent LABs within the same row together automatically. A carry chain  
can extend horizontally up to one full LAB row, but does not extend between LAB  
rows.  
Clear and Preset Logic Control  
LAB-wide signals control the logic for the registers clear and preset signals. The LE  
directly supports an asynchronous clear and preset function. The register preset is  
achieved through the asynchronous load of a logic high. MAX V devices support  
simultaneous preset/asynchronous load and clear signals. An asynchronous clear  
signal takes precedence if both signals are asserted simultaneously. Each LAB  
supports up to two clears and one preset signal.  
In addition to the clear and preset ports, MAX V devices provide a chip-wide reset pin  
(
DEV_CLRn) that resets all registers in the device. An option set before compilation in  
the Quartus II software controls this pin. This chip-wide reset overrides all other  
control signals and uses its own dedicated routing resources without using any of the  
four global resources. Driving this signal low before or during power-up prevents  
user mode from releasing clears within the design. This allows you to control when  
clear is released on a device that has just been powered-up. If not set for its chip-wide  
reset function, the DEV_CLRnpin is a regular I/O pin.  
By default, all registers in MAX V devices are set to power-up low. However, this  
power-up state can be set to high on individual registers during design entry using  
the Quartus II software.  
LE RAM  
The Quartus II memory compiler can configure the unused LEs as LE RAM.  
MAX V devices support the following memory types:  
FIFO synchronous R/W  
FIFO asynchronous R/W  
1 port SRAM  
2 port SRAM  
3 port SRAM  
shift registers  
f For more information about memory, refer to the Internal Memory (RAM and ROM)  
User Guide.  
December 2010 Altera Corporation  
MAX V Device Handbook  
 复制成功!