3–10
Chapter 3: DC and Switching Characteristics for MAX V Devices
Power Consumption
Power Consumption
You can use the Altera
®
PowerPlay Early Power Estimator and PowerPlay Power
Analyzer to estimate the device power.
f
For more information about these power analysis tools, refer to the
and the
chapter
in volume 3 of the
Quartus II Handbook.
Timing Model and Specifications
MAX V devices timing can be analyzed with the Altera Quartus
®
II software, a variety
of industry-standard EDA simulators and timing analyzers, or with the timing model
shown in
MAX V devices have predictable internal delays that allow you to determine the
worst-case timing of any design. The software provides timing simulation,
point-to-point delay prediction, and detailed timing analysis for device-wide
performance evaluation.
Figure 3–2. Timing Model for MAX V Devices
Output and Output Enable
Data Delay
t
R4
Data-In/LUT Chain
User
Flash
Memory
Logic Element
LUT Delay
t
IODR
t
IOE
t
C4
Output Routing
Delay
t
LOCAL
t
LUT
Register Control
Delay
t
COMB
t
CO
t
SU
t
H
t
PRE
t
CLR
t
FASTIO
I/O Input Delay
t
IN
Input Routing
Delay
t
DL
Output
Delay
t
OD
t
XZ
t
ZX
I/O Pin
t
C
I/O Pin
INPUT
t
GLOB
Global Input Delay
To Adjacent LE
Register Delays
From Adjacent LE
Combinational Path Delay
Data-Out
You can derive the timing characteristics of any signal path from the timing model
and parameters of a particular device. You can calculate external timing parameters,
which represent pin-to-pin timing delays, as the sum of the internal parameters.
f
For more information, refer to
May 2011
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
