Chapter 3: DC and Switching Characteristics for MAX V Devices
3–29
Timing Model and Specifications
JTAG Timing Specifications
Figure 3–6 shows the timing waveform for the JTAG signals for the MAX V device
family.
Figure 3–6. JTAG Timing Waveform for MAX V Devices
TMS
TDI
t
JCP
t
t
JPH
JPSU
t
t
JCL
JCH
TCK
TDO
t
t
t
JPXZ
JPZX
JPCO
t
t
JSSU
JSH
Signal
to be
Captured
t
t
t
JSXZ
JSZX
JSCO
Signal
to be
Driven
Table 3–41 lists the JTAG timing parameters and values for the MAX V device family.
Table 3–41. JTAG Timing Parameters for MAX V Devices (Part 1 of 2)
Symbol
Parameter
TCKclock period for VCCIO1 = 3.3 V
TCKclock period for VCCIO1 = 2.5 V
TCKclock period for VCCIO1 = 1.8 V
TCKclock period for VCCIO1 = 1.5 V
TCKclock high time
Min
55.5
62.5
100
143
20
Max
—
—
—
—
—
—
—
—
15
15
15
—
—
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tJCP (1)
tJCH
tJCL
TCK clock low time
20
tJPSU
tJPH
JTAG port setup time (2)
8
JTAG port hold time
10
tJPCO
tJPZX
tJPXZ
tJSSU
tJSH
JTAG port clock to output (2)
JTAG port high impedance to valid output (2)
JTAG port valid output to high impedance (2)
Capture register setup time
—
—
—
8
Capture register hold time
10
tJSCO
tJSZX
Update register clock to output
Update register high impedance to valid output
—
—
May 2011 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
