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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 3: DC and Switching Characteristics for MAX V Devices  
3–27  
Timing Model and Specifications  
LVDS and RSDS Output Timing Specifications  
Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.  
Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices  
5M40Z/ 5M80Z/ 5M160Z/  
5M240Z/ 5M570Z/5M1270Z/  
5M2210Z  
Parameter  
Mode  
Unit  
C4, C5, I5  
Min  
Max  
304  
304  
304  
304  
304  
304  
304  
304  
304  
304  
55  
10  
9  
8  
7  
6  
5  
4  
3  
2  
1  
45  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
Mbps  
%
Data rate (1), (2)  
tDUTY  
Total jitter (3)  
tRISE  
0.2  
UI  
450  
450  
ps  
tFALL  
ps  
Notes to Table 3–39:  
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R  
I/O buffer or 2x (FMAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through  
the Quartus II timing analysis of the complete design.  
(2) For the input clock pin to achieve 304 Mbps, use I/O standard with VCCIO of 2.5 V and above.  
(3) This specification is based on external clean clock source.  
May 2011 Altera Corporation  
MAX V Device Handbook  
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