Chapter 3: DC and Switching Characteristics for MAX V Devices
3–27
Timing Model and Specifications
LVDS and RSDS Output Timing Specifications
Table 3–39 lists the emulated LVDS output timing specifications for MAX V devices.
Table 3–39. Emulated LVDS Output Timing Specifications for MAX V Devices
5M40Z/ 5M80Z/ 5M160Z/
5M240Z/ 5M570Z/5M1270Z/
5M2210Z
Parameter
Mode
Unit
C4, C5, I5
Min
Max
304
304
304
304
304
304
304
304
304
304
55
10
9
8
7
6
5
4
3
2
1
—
—
—
—
—
—
—
—
—
—
—
—
—
—
45
—
—
—
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
%
Data rate (1), (2)
tDUTY
Total jitter (3)
tRISE
0.2
UI
450
450
ps
tFALL
ps
Notes to Table 3–39:
(1) The performance of the LVDS_E_3R transmitter system is limited by the lower of the two—the maximum data rate supported by LVDS_E_3R
I/O buffer or 2x (FMAX of the ALTLVDS_TX instance). The actual performance of your LVDS_E_3R transmitter system must be attained through
the Quartus II timing analysis of the complete design.
(2) For the input clock pin to achieve 304 Mbps, use I/O standard with VCCIO of 2.5 V and above.
(3) This specification is based on external clean clock source.
May 2011 Altera Corporation
MAX V Device Handbook
ALTERA [ ALTERA CORPORATION ]
