2–30
Chapter 2: MAX V Architecture
I/O Structure
Table 2–4. MAX V I/O Standards (Part 2 of 2)
I/O Standard
Output Supply Voltage (VCCIO
)
Type
(V)
3.3-V PCI (1)
LVDS (2)
Single-ended
Differential
Differential
3.3
2.5
2.5
RSDS (3)
Notes to Table 2–4:
(1) The 3.3-V PCI compliant I/O is supported in Bank 3 of the 5M1270Z and 5M2210Z devices.
(2) MAX V devices only support emulated LVDS output using a three resistor network (LVDS_E_3R).
(3) MAX V devices only support emulated RSDS output using a three resistor network (RSDS_E_3R).
The 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z devices support two I/O banks,
as shown in Figure 2–22. Each of these banks support all the LVTTL, LVCMOS, LVDS,
and RSDS standards shown in Table 2–4. PCI compliant I/O is not supported in these
devices and banks.
Figure 2–22. I/O Banks for 5M40Z, 5M80Z, 5M160Z, 5M240Z, and 5M570Z Devices (Note 1), (2)
I/O Bank 1
I/O Bank 2
All I/O Banks Support
3.3-V LVTTL/LVCMOS,
2.5-V LVTTL/LVCMOS,
1.8-V LVTTL/LVCMOS,
1.5-V LVCMOS,
1.2-V LVCMOS (3),
LVDS (4),
RSDS (5)
Notes to Figure 2–22:
(1) Figure 2–22 is a top view of the silicon die.
(2) Figure 2–22 is a graphical representation only. Refer to the pin list and the Quartus II software for exact pin locations.
(3) This I/O standard is not supported in Bank 1.
(4) Emulated LVDS output using a three resistor network (LVDS_E_3R).
(5) Emulated RSDS output using a three resistor network (RSDS_E_3R).
MAX V Device Handbook
December 2010 Altera Corporation
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