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5M160ZT100I5 参数 Datasheet PDF下载

5M160ZT100I5图片预览
型号: 5M160ZT100I5
PDF下载: 下载PDF文件 查看货源
内容描述: [Flash PLD, 14ns, PQFP100, 16 X 16 MM, 0.50 MM PITCH, TQFP-100]
分类和应用: 时钟可编程逻辑
文件页数/大小: 166 页 / 4004 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: MAX V Architecture  
2–27  
I/O Structure  
Fast I/O Connection  
A dedicated fast I/O connection from the adjacent LAB to the IOEs within an I/O  
block provides faster output delays for clock-to-output and tPD propagation delays.  
This connection exists for data output signals, not output enable signals or input  
signals. Figure 2–20, Figure 2–21, and Figure 2–22 illustrate the fast I/O connection.  
Figure 2–19. IOE Structure for MAX V Devices  
Data_in Fast_out  
Data_out OE  
DEV_OE  
Optional  
PCI Clamp (1)  
Programmable  
Pull-Up (2)  
V
V
CCIO  
CCIO  
I/O Pin  
Optional Bus-Hold  
Circuit  
Drive Strength Control  
Open-Drain Output  
Slew Control  
Optional Schmitt  
Trigger Input  
Programmable  
Input Delay  
Notes to Figure 2–19:  
(1) Available only in I/O bank 3 of 5M1270Z and 5M2210Z devices.  
(2) The programmable pull-up resistor is active during power-up, in-system programming (ISP), and if the device is unprogrammed.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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