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5M1270ZT64A4N 参数 Datasheet PDF下载

5M1270ZT64A4N图片预览
型号: 5M1270ZT64A4N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–34  
Chapter 2: MAX V Architecture  
I/O Structure  
Slew-Rate Control  
The output buffer for each MAX V device I/O pin has a programmable output  
slew-rate control that can be configured for low noise or high-speed performance. A  
faster slew rate provides high-speed transitions for high-performance systems.  
However, these fast transitions may introduce noise transients into the system. A slow  
slew rate reduces system noise, but adds a nominal output delay to rising and falling  
edges. The lower the voltage standard (for example, 1.8-V LVTTL) the larger the  
output delay when slow slew is enabled. Each I/O pin has an individual slew-rate  
control, allowing you to specify the slew rate on a pin-by-pin basis. The slew-rate  
control affects both the rising and falling edges. If no slew-rate control is specified, the  
Quartus II software defaults to a fast slew rate.  
1
The slew-rate control feature can be used simultaneously with the programmable  
drive strength feature.  
Open-Drain Output  
MAX V devices provide an optional open-drain (equivalent to open-collector) output  
for each I/O pin. This open-drain output enables the device to provide system-level  
control signals (for example, interrupt and write enable signals) that can be asserted  
by any of several devices. This output can also provide an additional wired-OR plane.  
Programmable Ground Pins  
Each unused I/O pin on MAX V devices can be used as an additional ground pin.  
This programmable ground feature does not require the use of the associated LEs in  
the device. In the Quartus II software, unused pins can be set as programmable GND  
on a global default basis or they can be individually assigned. Unused pins also have  
the option of being set as tri-stated input pins.  
Bus-Hold  
Each MAX V device I/O pin provides an optional bus-hold feature. The bus-hold  
circuitry can hold the signal on an I/O pin at its last-driven state. Because the bus-  
hold feature holds the last-driven state of the pin until the next input signal is present,  
an external pull-up or pull-down resistor is not necessary to hold a signal level when  
the bus is tri-stated.  
The bus-hold circuitry also pulls un-driven pins away from the input threshold  
voltage where noise can cause unintended high-frequency switching. You can select  
this feature individually for each I/O pin. The bus-hold output will drive no higher  
than VCCIO to prevent overdriving signals. If the bus-hold feature is enabled, the  
device cannot use the programmable pull-up option.  
The bus-hold circuitry is only active after the device has fully initialized. The bus-hold  
circuit captures the value on the pin present at the moment user mode is entered.  
MAX V Device Handbook  
December 2010 Altera Corporation  
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