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5M1270ZT64A4N 参数 Datasheet PDF下载

5M1270ZT64A4N图片预览
型号: 5M1270ZT64A4N
PDF下载: 下载PDF文件 查看货源
内容描述: MAX V器件手册 [MAX V Device Handbook]
分类和应用:
文件页数/大小: 166 页 / 4016 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: MAX V Architecture  
2–33  
I/O Structure  
Output Enable Signals  
Each MAX V IOE output buffer supports output enable signals for tri-state control.  
The output enable signal can originate from the GCLK[3..0]global signals or from the  
MultiTrack interconnect. The MultiTrack interconnect routes output enable signals  
and allows for a unique output enable for each output or bidirectional pin.  
MAX V devices also provide a chip-wide output enable pin (DEV_OE) to control the  
output enable for every output pin in the design. An option set before compilation in  
the Quartus II software controls this pin. This chip-wide output enable uses its own  
routing resources and does not use any of the four global resources. If this option is  
turned on, all outputs on the chip operate normally when DEV_OEis asserted. When  
the pin is deasserted, all outputs are tri-stated. If this option is turned off, the DEV_OE  
pin is disabled when the device operates in user mode and is available as a user I/O  
pin.  
Programmable Drive Strength  
The output buffer for each MAX V device I/O pin has two levels of programmable  
drive strength control for each of the LVTTL and LVCMOS I/O standards.  
Programmable drive strength provides system noise reduction control for high  
performance I/O designs. Although a separate slew-rate control feature exists, using  
the lower drive strength setting provides signal slew-rate control to reduce system  
noise and signal overshoot without the large delay adder associated with the  
slew-rate control feature. Table 2–7 lists the possible settings for the I/O standards  
with drive strength control. The Quartus II software uses the maximum current  
strength as the default setting. The PCI I/O standard is always set at 20 mA with no  
alternate setting.  
Table 2–7. Programmable Drive Strength (Note 1)  
I/O Standard  
3.3-V LVTTL  
IOH/IOL Current Strength Setting (mA)  
16  
8
8
3.3-V LVCMOS  
4
14  
7
2.5-V LVTTL/LVCMOS  
1.8-V LVTTL/LVCMOS  
1.5-V LVCMOS  
6
3
4
2
1.2-V LVCMOS  
3
Note to Table 2–7:  
(1) The IOH current strength numbers shown are for a condition of a VOUT = VOH minimum, where the VOH  
minimum is specified by the I/O standard. The IOL current strength numbers shown are for a condition of a  
VOUT = VOL maximum, where the VOL maximum is specified by the I/O standard. For 2.5-V LVTTL/LVCMOS,  
the IOH condition is VOUT = 1.7 V and the IOL condition is VOUT = 0.7 V.  
1
The programmable drive strength feature can be used simultaneously with the  
slew-rate control feature.  
December 2010 Altera Corporation  
MAX V Device Handbook  
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