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Chapter 2: MAX V Architecture
I/O Structure
I/O Structure
IOEs support many features, including:
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LVTTL, LVCMOS, LVDS, and RSDS I/O standards
3.3-V, 32-bit, 33-MHz PCI compliance
JTAG boundary-scan test (BST) support
Programmable drive strength control
Weak pull-up resistors during power-up and in system programming
Slew-rate control
Tri-state buffers with individual output enable control
Bus-hold circuitry
Programmable pull-up resistors in user mode
Unique output enable per pin
Open-drain outputs
Schmitt trigger inputs
Fast I/O connection
Programmable input delay
MAX V device IOEs contain a bidirectional I/O buffer. Figure 2–19 shows the MAX V
IOE structure. Registers from adjacent LABs can drive to or be driven from the IOE’s
bidirectional I/O buffers. The Quartus II software automatically attempts to place
registers in the adjacent LAB with fast I/O connection to achieve the fastest possible
clock-to-output and registered output enable timing. When the fast input registers
option is enabled, the Quartus II software automatically routes the register to
guarantee zero hold time. You can set timing assignments in the Quartus II software
to achieve desired I/O timing.
MAX V Device Handbook
December 2010 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
