1. Overview for Cyclone V Device Family
February 2012
CV-51001-1.2
CV-51001-1.2
Cyclone® V devices are designed to simultaneously accommodate the shrinking
power consumption, cost, and time-to-market requirements; and the increasing
bandwidth requirements for high-volume and cost-sensitive applications.
The Cyclone V devices are ideal for small form factor applications that are cost- and
power-sensitive in the wireless, wireline, military, broadcast, industrial, consumer,
and communications industries.
The Cyclone V device family is available in six variants:
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Cyclone V E—optimized for the lowest system cost and power requirement for a
wide spectrum of general logic and digital signal processing (DSP) applications.
Cyclone V GX—optimized for the lowest cost and power requirement for
614-megabits per second (Mbps) to 3.125-gigabits per second (Gbps) transceiver
applications.
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Cyclone V GT—the FPGA industry’s lowest cost and lowest power requirement
for 5-Gbps transceiver applications.
Cyclone V SE—system-on-a-chip (SoC) FPGA with integrated Cyclone V FPGA
and ARM®-based hard processor system (HPS).
Cyclone V SX—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,
and 3.125-Gbps transceivers.
Cyclone V ST—SoC FPGA with integrated Cyclone V FPGA, ARM-based HPS,
and 5-Gbps transceivers.
The Cyclone V SoC FPGA variants feature an FPGA integrated with an HPS that
consists of a dual-core ARM Cortex™-A9 MPCore™ processor, a rich set of peripherals,
and a shared multiport SDRAM controller.
The Cyclone V device family provides the following key advantages:
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Up to 40% lower power consumption than the previous generation device—built
on TSMC’s 28-nm low power (28LP) process and includes an abundance of hard
intellectual properties (IP).
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Improved logic integration and differentiation capabilities—features a new
8-input adaptive logic module (ALM), up to 11.6 megabits (Mb) of dedicated
memory, and variable-precision DSP blocks.
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Increased bandwidth capacity—a combined result of the new 3-Gbps and 5-Gbps
transceivers, and the hard memory controllers.
Tight integration of a dual-core ARM Cortex-A9 MPCore processor, hard IP, and
an FPGA in a single Cyclone V SoC FPGA—supports over 100 Gbps peak
bandwidth with integrated data coherency between the processor and the FPGA.
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Cyclone V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012
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