Electrical Characteristics
Page 5
Table 3. Recommended Operating Conditions for Cyclone V Devices—Preliminary (Part 2 of 2)
Symbol
t
RAMP
Description
Power supply ramp time
Condition
Standard POR
Fast POR
Minimum
200 µs
200 µs
Typical
—
—
Maximum
100 ms
4 ms
Unit
—
—
Notes to
(1) V
CCPD
must be 2.5 V when V
CCIO
is 2.5, 1.8, 1.5, 1.35, 1.25 or 1.2 V. V
CCPD
must be 3.0 V when V
CCIO
is 3.0 V. V
CCPD
must be 3.3 V when V
CCIO
is 3.3 V.
(2) PLL digital voltage is regulated from V
CCA_FPLL
.
(3) If you do not use the design security feature in Cyclone V devices, connect V
CCBAT
to a 1.5-V, 2.5-V, or 3.0-V power supply. The power-on reset
(POR) circuitry monitors V
CCBAT
. Cyclone V devices do not exit POR if V
CCBAT
stays low.
(4) This is also applicable to HPS power supply. For HPS power supply, refer to t
RAMP
specifications for standard POR when HPS_PORSEL = 0 and
t
RAMP
specifications for fast POR when HPS_PORSEL = 1.
lists the transceiver power supply recommended operating conditions for
Cyclone V GX and GT devices.
Table 4. Transceiver Power Supply Operating Conditions for Cyclone V GX and GT Devices—Preliminary
Symbol
V
CCH_GXBL
V
CCE_GXBL
V
CCL_GXBL
Notes to
(1) Altera recommends increasing the V
CCE_GXBL
and V
CCL_GXBL
typical value from 1.1 V to 1.2 V for Cyclone V GT FPGA systems which require full
compliance to the PCIe Gen2 transmit jitter specification. For more information about the maximum full duplex channels recommended in
Cyclone V GT and ST devices under this condition, refer to the
chapter.
(2) Altera recommends increasing the V
CCE_GXBL
and V
CCL_GXBL
typical value from 1.1 V to 1.2 V for full compliance to CPRI transmit jitter
specification at 4.9152 Gbps (Cyclone V GT and ST devices) and 6.144Gbps (Cyclone V GT devices only). For more information about the
maximum full duplex channels recommended in Cyclone V GT devices for CPRI 6.144 Gbps, refer to the
chapter.
Description
Transceiver high voltage power (left side)
Transmitter and receiver power (left side)
Clock network power (left side)
Minimum
2.375
1.07/1.17
1.07/1.17
Typical
2.5
1.1/1.2
1.1/1.2
Maximum
2.625
1.13/1.23
1.13/1.23
Unit
V
V
V
lists the steady-state voltage values expected from Cyclone V
system-on-a-chip (SoC) FPGA with ARM
®
-based hard processor system (HPS). Power
supply ramps must all be strictly monotonic, without plateaus.
Table 5. HPS Power Supply Operating Conditions for Cyclone V SE, SX, and ST Devices
—Preliminary
(Part 1 of 2)
Symbol
V
CC_HPS
Description
HPS core voltage and periphery circuitry power
supply
HPS I/O pre-driver (3.3 V) power supply
V
CCPD_HPS
HPS I/O pre-driver (3.0 V) power supply
HPS I/O pre-driver (2.5 V) power supply
HPS I/O buffers (3.3 V) power supply
HPS I/O buffers (3.0 V) power supply
V
CCIO_HPS
HPS I/O buffers (2.5 V) power supply
HPS I/O buffers (1.8 V) power supply
HPS I/O buffers (1.5 V) power supply
HPS I/O buffers (1.2 V) power supply
Minimum
1.07
3.135
2.85
2.375
3.135
2.85
2.375
1.71
1.425
1.14
Typical
1.1
3.3
3.0
2.5
3.3
3.0
2.5
1.8
1.5
1.2
Maximum
1.13
3.465
3.15
2.625
3.465
3.15
2.625
1.89
1.575
1.26
Unit
V
V
V
V
V
V
V
V
V
V
June 2013 Altera Corporation
Cyclone V Device Datasheet
ALTERA [ ALTERA CORPORATION ]
