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5ASXMB3E4F31I3N 参数 Datasheet PDF下载

5ASXMB3E4F31I3N图片预览
型号: 5ASXMB3E4F31I3N
PDF下载: 下载PDF文件 查看货源
内容描述: [Field Programmable Gate Array, 670MHz, PBGA896, ROHS COMPLIANT, FBGA-896]
分类和应用: 时钟LTE可编程逻辑
文件页数/大小: 184 页 / 1809 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51002  
2017.02.10  
1-30  
Transceiver Specifications for Arria V GT and ST Devices  
Transceiver Speed Grade 3  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
Max  
–50  
10 Hz  
100 Hz  
1 KHz  
10 KHz  
100 KHz  
≥ 1 MHz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
Ω
–80  
–110  
–120  
–120  
–130  
Transmitter REFCLKphase noise(43)  
RREF  
2000 1%  
Table 1-27: Transceiver Clocks Specifications for Arria V GT and ST Devices  
Transceiver Speed Grade 3  
Symbol/Description  
Condition  
Unit  
Min  
Typ  
125  
Max  
fixedclkclock frequency  
PCIe Receiver Detect  
MHz  
MHz  
Transceiver Reconfiguration  
Controller IP (mgmt_clk_clk) clock  
frequency  
75  
125  
Table 1-28: Receiver Specifications for Arria V GT and ST Devices  
Transceiver Speed Grade 3  
Typ  
Symbol/Description  
Condition  
Unit  
Min  
Max  
Supported I/O Standards  
Data rate (6-Gbps transceiver)(44)  
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS  
611 6553.6  
Mbps  
(43)  
(44)  
e transmitter REFCLKphase jitter is 30 ps p-p (5 ps RMS) with bit error rate (BER) 10-12, equivalent to 14 sigma.  
To support data rates lower than the minimum specification through oversampling, use the CDR in LTR mode only.  
Arria V GX, GT, SX, and ST Device Datasheet  
Send Feedback  
Altera Corporation  
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