AV-51002
2017.02.10
1-29
Transceiver Specifications for Arria V GT and ST Devices
Transceiver Specifications for Arria V GT and ST Devices
Table 1-26: Reference Clock Specifications for Arria V GT and ST Devices
Transceiver Speed Grade 3
Typ
Symbol/Description
Condition
Unit
Min
Max
Supported I/O standards
1.2 V PCML, 1.4 VPCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL(40), HCSL, and LVDS
Input frequency from REFCLKinput
—
27
—
—
—
—
—
710
400
400
MHz
pins
Rise time
Measure at 60 mV of
ps
differential signal(41)
Fall time
Measure at 60 mV of
ps
differential signal(41)
Duty cycle
—
—
45
200
30
—
—
—
55
300(42)/2000
33
%
Peak-to-peak differential input voltage
mV
kHz
Spread-spectrum modulating clock
frequency
PCI Express (PCIe)
Spread-spectrum downspread
On-chip termination resistors
VICM (AC coupled)
PCIe
—
—
—
0 to –0.5%
—
—
—
Ω
100
1.2
—
—
—
—
V
VICM (DC coupled)
HCSL I/O standard for the PCIe
reference clock
250
550
mV
(40)
(41)
(42)
Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.
REFCLKperformance requires to meet transmitter REFCLKphase noise specification.
e maximum peak-to peak differential input voltage of 300 mV is allowed for DC coupled link.
Arria V GX, GT, SX, and ST Device Datasheet
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