AV-51002
2017.02.10
1-22
Differential I/O Standard Specifications
VCCIO (V)
VID (mV)(16)
Condition
VICM(DC) (V)
Condition
VOD (V)(17)
Typ
VOCM (V)(17)(18)
Min Typ Max
I/O Standard
Min
Typ
Max
Min
Max
Min
Max
Min
Max
PCML
Transmitter, receiver, and input reference clock pins of high-speed transceivers use the PCML I/O standard. For transmitter, receiver, and
reference clock I/O pin specifications, refer to Transceiver Specifications for Arria V GX and SX Devices and Transceiver Specifications
for Arria V GT and ST Devices tables.
—
0.05
1.05
0.25
0.300
0.60
1.00
DMAX
≤
1.80
1.55
1.45
1.25 Gbps
2.5 V
VCM
=
2.375
2.375
2.5
2.625
100
0.247
0.1
—
0.6
1.125 1.25
1.375
LVDS(19)
1.25 V
—
DMAX
>
1.25 Gbps
—
RSDS
2.5
2.5
2.625
2.625
100
200
VCM
=
—
0.2
—
0.6
0.6
0.5
1
1.2
1.2
1.4
1.4
(HIO)(20)
1.25 V
—
Mini-LVDS 2.375
(HIO)(21)
600
—
1.425 0.25
DMAX
≤
1.80
700 Mbps
LVPECL(22)
—
—
—
300
—
—
—
—
—
—
—
—
DMAX
>
1.60
700 Mbps
Related Information
•
Transceiver Specifications for Arria V GX and SX Devices on page 1-23
Provides the specifications for transmitter, receiver, and reference clock I/O pin.
(16)
(17)
(18)
(19)
e minimum VID value is applicable over the entire common mode range, VCM
RL range: 90 ≤ RL ≤ 110 Ω.
.
is applies to default pre-emphasis setting only.
For optimized LVDS receiver performance, the receiver voltage input range must be within 1.0 V to 1.6 V for data rates above 1.25 Gbps and 0 V to
1.85 V for data rates below 1.25 Gbps.
For optimized RSDS receiver performance, the receiver voltage input range must be within 0.25 V to 1.45 V.
For optimized Mini-LVDS receiver performance, the receiver voltage input range must be within 0.3 V to 1.425 V.
For optimized LVPECL receiver performance, the receiver voltage input range must be within 0.85 V to 1.75 V for data rates above 700 Mbps and 0.45
V to 1.95 V for data rates below 700 Mbps.
(20)
(21)
(22)
Arria V GX, GT, SX, and ST Device Datasheet
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