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5AGXMD3G631I4N 参数 Datasheet PDF下载

5AGXMD3G631I4N图片预览
型号: 5AGXMD3G631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–19  
Switching Characteristics  
(1)  
Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary  
(Part 2 of 2)  
–5  
Industrial  
Speed Grade  
Symbol/  
Conditions  
Description  
Unit  
Min  
Typ  
Max  
PCIe (Gen1 and Gen2),  
GIGE, XAUI, SDI, CPRI,  
OBSAI, SFI  
Differential and common mode return loss  
Compliant  
62.5, 100, 125, 200, 250, 300, 500,  
and 1000  
(6)  
Programmable ppm detector  
ppm  
Run Length  
0
200  
4
UI  
dB  
dB  
dB  
Programmable equalization  
DC Gain Setting = 0  
DC Gain Setting = 1  
Programmable DC gain  
3
Transmitter  
Supported I/O Standards  
Data rate (6-Gbps transceiver)  
Data rate (10-Gbps transceiver)  
VOCM  
1.5 V PCML  
611  
6.376  
9.8304  
650  
85  
6375  
10.3125  
Mbps  
Gbps  
mV  
85-setting  
100-setting  
120-setting  
150-setting  
100  
120  
150  
Differential on-chip termination resistors  
(7)  
Rise time  
30  
160  
160  
ps  
(7)  
Fall time  
30  
ps  
CMU PLL  
Supported data range  
0.611  
10.3125  
Gbps  
Transceiver-FPGA Fabric Interface  
Interface speed (80-bit mode)  
25  
25  
25  
159.375  
156.25  
MHz  
MHz  
MHz  
Interface speed  
(single-width mode)  
Interface speed (double-width mode)  
159.375  
Notes to Table 2–21:  
(1) Speed grades shown in Table 2–21 refer to the Transceiver Speed Grade in the device ordering code. For more information about device  
ordering codes, refer to the Overview for Arria V Device Family chapter.  
(2) Differential LVPECL signal levels must comply to the minimum and maximum peak-to-peak differential input voltage specified in this table.  
(3) The reference clock common mode voltage is equal to the VCCR_GXB power supply level.  
(4) The device cannot tolerate prolonged operation at this absolute maximum.  
(5) The differential eye opening specification at the receiver input pins assumes that you have disabled the Receiver Equalization feature. If you  
enable the Receiver Equalization feature, the receiver circuitry can tolerate a lower minimum eye opening, depending on the equalization level.  
(6) The rate match FIFO supports only up to 300 ppm.  
(7) The Quartus II software automatically selects the appropriate slew rate depending on the configured data rate or functional mode.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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