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5AGXMD3G631I4N 参数 Datasheet PDF下载

5AGXMD3G631I4N图片预览
型号: 5AGXMD3G631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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2–18  
Chapter 2: Device Datasheet for Arria V Devices  
Switching Characteristics  
(1)  
Table 2–21. Transceiver Specifications for Arria V GT Devices—Preliminary  
(Part 1 of 2)  
–5  
Industrial  
Speed Grade  
Symbol/  
Conditions  
Description  
Unit  
Min  
Typ  
Max  
Reference Clock  
1.2 V PCML, 1.4 V PCML, 1.5 V PCML, 2.5 V PCML, Differential LVPECL (2)  
HCSL, and LVDS  
,
Supported I/O Standards  
Input frequency from REFCLKinput pins  
Duty cycle  
27  
45  
710  
55  
MHz  
%
Peak-to-peak differential input voltage  
200  
2000  
mV  
Spread-spectrum modulating clock  
frequency  
PCI Express® (PCIe®)  
30  
33  
kHz  
0 to  
–0.5%  
100  
Spread-spectrum downspread  
On-chip termination resistors  
PCIe  
(3)  
VICM (AC coupled)  
1.1  
V
HCSL I/O standard for  
the PCIe reference clock  
V
ICM (DC coupled)  
250  
550  
mV  
RREF  
2000 1%  
Transceiver Clocks  
PCIe  
Receiver Detect  
fixedclkclock frequency  
125  
MHz  
MHz  
Avalon-MM PHY management clock  
frequency  
< 150  
Receiver  
Supported I/O Standards  
Data rate (6-Gbps Transceiver)  
Data rate (10-Gbps transceiver)  
1.5 V PCML, 2.5 V PCML, LVPECL, and LVDS  
611  
6.376  
9.8304  
6375  
10.3125  
1.2  
Mbps  
Gbps  
V
(4)  
Absolute VMAX for a receiver pin  
Absolute VMIN for a receiver pin  
–0.4  
V
Maximum peak-to-peak differential input  
voltage VID (diff p-p) before device  
configuration  
1.6  
V
Maximum peak-to-peak differential input  
voltage VID (diff p-p) after device  
configuration  
85  
2.2  
V
Minimum differential eye opening at the  
mV  
(5)  
receiver serial input pins  
85-setting  
100-setting  
120-setting  
150-setting  
85  
100  
120  
150  
Differential on-chip termination resistors  
Arria V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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