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5AGXMA3D631C4N 参数 Datasheet PDF下载

5AGXMA3D631C4N图片预览
型号: 5AGXMA3D631C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
35  
Power Management  
interface. The Arria V CvP implementation conforms to the PCIe 100 ms power-up-to-active time  
requirement.  
Note: Although Arria V GZ devices support PCIe Gen3, you can use only PCIe Gen1 and PCIe Gen2 for  
CvP configuration scheme.  
Related Information  
Configuration via Protocol (CvP) Implementation in Altera FPGAs User Guide  
Provides more information about CvP.  
Power Management  
Leveraging the FPGA architectural features, process technology advancements, and transceivers that are  
designed for power efficiency, the Arria V devices consume less power than previous generation Arria FPGAs:  
Total device core power consumptionless by up to 50%.  
Transceiver channel power consumptionless by up to 50%.  
Additionally, Arria V devices contain several hard IP blocks, including PCIe Gen1, Gen2, and Gen3, GbE,  
SRIO, GPON, and CPRI protocols, that reduce logic resources and deliver substantial power savings of up  
to 25% less power than equivalent soft implementations.  
Document Revision History  
Date  
Version  
Changes  
May 2013  
2013.05.06 Moved all links to the Related Information section of respective topics  
for easy reference.  
Added link to the known document issues in the Knowledge Base.  
Updated the available options, maximum resource counts, and per  
package information for the Arria V SX and ST device variants.  
Updated the variable DSP multipliers counts for the Arria V SX and  
ST device variants.  
Clarified that partial reconfiguration is an advanced feature. Contact  
Altera for support of the feature.  
Added footnote to clarify that MLAB 64 bits depth is available only for  
Arria V GZ devices.  
Updated description about power-up sequence requirement for device  
migration to improve clarity.  
January 2013  
2013.01.11 Added the L optional suffix to the Arria V GZ ordering code for the  
I3 speed grade.  
Added a note about the power-up sequence requirement if you plan  
to migrate your design from the Arria V GX A5 and A7, and Arria V  
GT C7 devices to other Arria V devices.  
Arria V Device Overview  
Altera Corporation  
Feedback  
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