AV-51001
2013.05.06
31
System Peripherals and Debug Access Port
Figure 12: HPS with Dual-Core ARM Cortex-A9 MPCore Processor
Configuration
Controller
Lightweight
HPS-to-FPGA
FPGA Fabric
FPGA-to-HPS HPS-to-FPGA
FPGA-to-HPS SDRAM
FPGA
Manager
HPS
Debug
Access Port
MPU Subsystem
ARM Cortex-A9 MPCore
ETR
(Trace)
CPU0
ARM Cortex-A9
with NEON/FPU,
CPU1
Multiport
DDR SDRAM
Controller
with
ARM Cortex-A9
SD/MMC
Controller
with NEON/FPU,
32 KB Instruction Cache,
32 KB Data Cache, and
32 KB Instruction Cache,
32 KB Data Cache, and
Memory Management Unit Memory Management Unit
Ethernet
Optional ECC
MAC (2x)
Level 3
Interconnect
ACP
STM
SCU
USB
OTG (2x)
NAND Flash
Controller
Level 2 Cache (512 KB)
DMA
Controller
64 KB
Boot ROM
64 KB
On-Chip RAM
Peripherals
(UART, Timer, I 2C, Watchdog Timer, GPIO, SPI, Clock Manager, Reset Manager, Scan Manager, System Manager, and
Quad SPI Flash Controller)
System Peripherals and Debug Access Port
Each Ethernet MAC, USB OTG, NAND flash controller, and SD/MMC controller module has an integrated
DMA controller. For modules without an integrated DMA controller, an additional DMA controller module
provides up to eight channels of high-bandwidth data transfers. Peripherals that communicate off-chip are
multiplexed with other peripherals at the HPS pin level. This allows you to choose which peripherals to
interface with other devices on your PCB.
The debug access port provides interfaces to industry standard JTAG debug probes and supports ARM
CoreSight debug and core traces to facilitate software development.
Arria V Device Overview
Altera Corporation
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