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5AGXMA1D431C3ES 参数 Datasheet PDF下载

5AGXMA1D431C3ES图片预览
型号: 5AGXMA1D431C3ES
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件概述 [Arria V Device Overview]
分类和应用:
文件页数/大小: 37 页 / 793 K
品牌: ALTERA [ ALTERA CORPORATION ]
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AV-51001  
2013.05.06  
22  
External Memory Interface  
Figure 8: PCIe Multifunction for Arria V Devices  
External System  
FPGA Device  
Host CPU  
PCIe Link  
Root  
Complex  
Local  
Local  
Peripheral 1 Peripheral 2  
The Arria V PCIe hard IP operates independently from the core logic. This independent operation allows  
the PCIe link to wake up and complete link training in less than 100 ms while the Arria V device completes  
loading the programming file for the rest of the device.  
In addition, the PCIe hard IP in the Arria V device provides improved end-to-end datapath protection using  
ECC.  
External Memory Interface  
This section provides an overview of the external memory interface in Arria V devices.  
Hard and Soft Memory Controllers  
Arria V GX,GT, SX, and ST devices support up to four hard memory controllers for DDR3 and DDR2  
SDRAM devices. Each controller supports 8 to 32 bit components of up to 4 gigabits (Gb) in density with  
two chip selects and optional ECC. For the Arria V SoC FPGA devices, an additional hard memory controller  
in the HPS supports DDR3, DDR2, and LPDDR2 SDRAM devices.  
All Arria V devices support soft memory controllers for DDR3, DDR2, and LPDDR2 SDRAM devices, QDR  
II+, QDR II, and DDR II+ SRAM devices, and RLDRAM II devices for maximum flexibility.  
Note: DDR3 SDRAM leveling is supported only in Arria V GZ devices.  
External Memory Performance  
Table 18: External Memory Interface Performance in Arria V Devices  
Hard Controller (MHz)  
Soft Controller (MHz)  
Interface  
Voltage (V)  
Arria V GX, GT, SX, and Arria V GX, GT, SX, and  
Arria V GZ  
ST  
533  
533  
400  
ST  
1.5  
1.35  
1.8  
667  
667  
400  
400  
800  
800  
400  
DDR3 SDRAM  
DDR2 SDRAM  
LPDDR2 SDRAM  
RLDRAM 3  
1.2  
1.2  
667  
Arria V Device Overview  
Altera Corporation  
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