1–2
Chapter 1: Overview for the Arria V Device Family
Arria V Feature Summary
Arria V devices provide interface support flexibility with up to 10-Gbps transceivers,
1.25-Gbps
LVDS,
1.333-Gbps memory interfaces with low latency, and support for all
mainstream single-ended and differential I/O standards, including 3.3 V. Arria V
devices also offer the lowest system cost by requiring only three power supplies to
operate the devices and a thermal composite flip chip ball-grid array (BGA)
packaging option. Arria V devices also support innovative features, such as
configuration via protocol (CvP), partial reconfiguration, and design security.
Arria V devices provide the power, features, and cost you require to succeed with
your designs. With these innovations, Arria V devices deliver ideal performance and
capability for a wide range of applications.
Arria V Feature Summary
lists the Arria V device features.
Table 1–1. Feature Summary for Arria V Devices (Part 1 of 3)
Feature
■
Details
28-nm TSMC low-power process technology
Lowest static power in its class (less than 800 mW for 500 K logic elements (LEs) at 85°C
junction under typical conditions)
1.1-V core nominal voltage
611-Mbps to 10.3125-Gbps integrated transceivers
Transmit pre-emphasis and receiver equalization
Dynamic reconfiguration of individual channels
1.25-Gbps
LVDS
667-MHz/1.333-Gbps external memory interface
On-chip termination (OCT)
3.3-V support
Custom implementation up to 10.3125 Gbps
PCI Express
®
(PCIe
®
) Gen1 and Gen2
Gbps Ethernet (GbE) and XAUI physical coding sublayer (PCS)
Common Public Radio Interface (CPRI) PCS
Gigabit-capable passive optical network (GPON) PCS
Technology
■
■
Lowest-power serial
transceivers of any
midrange FPGA
■
■
■
■
FPGA General-purpose
I/Os (GPIOs)
■
■
■
■
■
Embedded transceiver
hard IP
■
■
■
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
February 2012 Altera Corporation
ALTERA [ ALTERA CORPORATION ]
