Chapter 2: Device Datasheet for Arria V Devices
2–39
Configuration Specification
(1)
Figure 2–5. DCLK-to-DATA[] FPP Configuration Timing Waveform When the Ratio is 1
tCF2ST1
tCFG
tCF2CK
nCONFIG
nSTATUS (2)
tSTATUS
(6)
tCF2ST0
tCLK
CONF_DONE (3)
t
CH tCL
tCF2CD
tST2CK
(4)
DCLK
tDH
Word 0 Word 1 Word 2 Word 3
Word n
DATA[15..0](5)
Word n-2 Word n-1
User Mode
User Mode
tDSU
High-Z
User I/O
(7)
INIT_DONE
tCD2UM
Notes to Figure 2–5:
(1) The beginning of this waveform shows the device in user mode. In user mode, nCONFIG
, nSTATUS, and CONF_DONEare at logic-high levels. When
nCONFIGis pulled low, a reconfiguration cycle begins.
(2) After power up, the Arria V device holds nSTATUSlow for the time of the POR delay.
(3) After power up, before and during configuration, CONF_DONEis low.
(4) Do not leave DCLKfloating after configuration. You can drive it high or low, whichever is more convenient.
(5) For FPP x16, use DATA[15..0]. For FPP x8, use DATA[7..0]. DATA[15..0]are available as a user I/O pin after configuration. The state of this
pin depends on the dual-purpose pin settings.
(6) To ensure a successful configuration, send the entire configuration data to the Arria V device. CONF_DONEis released high when the Arria V device
receives all the configuration data successfully. After CONF_DONEgoes high, send two additional falling edges on DCLKto begin initialization and
enter user mode.
(7) After the option bit to enable the INIT_DONEpin is configured into the device, the INIT_DONE goes low.
February 2012 Altera Corporation
Arria V Device Handbook
Volume 1: Device Overview and Datasheet
ALTERA [ ALTERA CORPORATION ]
