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5AGXFD3G427C4N 参数 Datasheet PDF下载

5AGXFD3G427C4N图片预览
型号: 5AGXFD3G427C4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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Chapter 2: Device Datasheet for Arria V Devices  
2–37  
Configuration Specification  
Configuration Specification  
This section provides configuration specifications and timing for Arria V devices.  
These characteristics can be designated as Preliminary or Final.  
Preliminary characteristics are created using simulation results, process data, and  
other known parameters. The title of these tables show the designation as  
“Preliminary.”  
Final numbers are based on actual silicon characterization and testing. The  
numbers reflect the actual performance of the device under worst-case silicon  
process, voltage, and junction temperature conditions. There are no designations  
on finalized tables.  
POR Specifications  
Table 2–36 lists the specifications for fast and standard POR for Arria V devices.  
Table 2–36. Fast and Standard POR Delay Specification for Arria V Devices (1)  
POR Delay  
Fast (2)  
Minimum (ms)  
Maximum (ms)  
4
12  
Standard (3)  
100  
300  
Notes to Table 2–36:  
(1) Select the POR delay based on the MSEL setting as described in the “Configuration Schemes for Arria V Devices”  
table in the Configuration, Design Security, and Remote System Upgrades in Arria V Devices chapter.  
(2) When the PORSELsignal is high, the device is in fast POR delay.  
(3) When the PORSELsignal is low, the device is in standard POR delay.  
JTAG Configuration Timing  
Table 2–37 lists the JTAG timing parameters and values for Arria V devices.  
Table 2–37. JTAG Timing Parameters and Values for Arria V Devices—Preliminary  
Symbol  
Description  
TCK clock period  
Min  
30  
14  
14  
1
Max  
Unit  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tJCP  
tJCH  
tJCL  
TCK clock high time  
TCK clock low time  
tJPSU (TDI)  
tJPSU (TMS)  
tJPH  
TDI JTAG port setup time  
TMS JTAG port setup time  
JTAG port hold time  
3
5
(1)  
tJPCO  
JTAG port clock to output  
JTAG port high impedance to valid output  
JTAG port valid output to high impedance  
11  
14  
14  
(1)  
(1)  
tJPZX  
tJPXZ  
Note to Table 2–37:  
(1) A 1-ns adder is required for each VCCIO voltage step down from 3.0 V. For example, tJPCO = 12 ns if VCCIO of the TDO  
I/O bank = 2.5 V, or 13 ns if it equals 1.8 V.  
February 2012 Altera Corporation  
Arria V Device Handbook  
Volume 1: Device Overview and Datasheet  
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