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5AGTMD3D631I4N 参数 Datasheet PDF下载

5AGTMD3D631I4N图片预览
型号: 5AGTMD3D631I4N
PDF下载: 下载PDF文件 查看货源
内容描述: 阿里亚V器件手册 [Arria V Device Handbook]
分类和应用:
文件页数/大小: 82 页 / 1787 K
品牌: ALTERA [ ALTERA CORPORATION ]
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1–4  
Chapter 1: Overview for the Arria V Device Family  
Arria V Family Plan  
Table 1–1. Feature Summary for Arria V Devices (Part 3 of 3)  
Feature  
Details  
Partial and dynamic reconfigurations  
CvP  
Configuration via HPS  
Configuration  
Serial and parallel flash interface  
Enhanced advanced encryption standard (AES) design security features  
Tamper protection  
Remote system upgrade  
Thermal composite flip chip BGA packaging  
Multiple device densities with identical package footprints for seamless migration between  
Packaging  
different device densities  
Lead, lead-free (Pb-free), and RoHS-compliant options  
Arria V Family Plan  
Arria V devices offer various thermal composite flip chip BGA packaging options  
with differing price and performance points. Table 1–2 and Table 1–3 list the Arria V  
devices features.  
Table 1–2. Maximum Resource Counts for Arria V GX Devices —Preliminary  
Arria V GX Device  
Feature  
5AGXA1 5AGXA3 5AGXA5 5AGXA7 5AGXB1 5AGXB3 5AGXB5 5AGXB7  
ALMs  
LE (K)  
28,302  
75  
56,100  
148  
1,051  
873  
10,510  
396  
792  
10  
71,698  
190  
91,680 113,208 136,880 158,491 190,240  
242  
1,366  
1,448  
13,660  
800  
1,600  
12  
300  
1,510  
1,852  
15,100  
920  
1,840  
12  
362  
1,726  
2,098  
17,260  
1,045  
2,090  
12  
420  
2,054  
2,532  
20,540  
1,092  
2,184  
16  
504  
2,414  
2,906  
24,140  
1,139  
2,278  
16  
M10K memory blocks  
MLAB memory (Kbit)  
Block memory (Kbit)  
Variable-precision DSP blocks  
18 x 19 multipliers  
Fractional PLLs (1)  
800  
463  
8,000  
240  
480  
10  
1,180  
1,173  
11,800  
600  
1,200  
12  
GPIO  
480  
68  
480  
68  
544  
544  
120  
136  
2
704  
160  
176  
2
704  
704  
704  
LVDS transmitter (TX) (2)  
LVDS receiver (RX) (2)  
PCIe hard IP blocks  
Hard memory controllers  
Notes to Table 1–2:  
120  
160  
156  
160  
80  
80  
136  
176  
172  
176  
1
1
2
2
2
2
2
2
4
4
4
4
4
4
(1) The total number of available fractional PLLs is a combination of general-purpose and transceiver PLLs. Transceiver fractional PLLs that are  
not used by the transceiver I/O can be used as general-purpose fractional PLLs.  
(2) For the LVDS channels count for each package, refer to the High-Speed Differential I/O Interfaces with DPA in Arria V Devices chapter.  
Arria V Device Handbook  
February 2012 Altera Corporation  
Volume 1: Device Overview and Datasheet  
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